An example of a component built-in wiring board in which plural kinds of components are buried and mounted in mixture is described in JP-A 2003-197849 (KOKAI). The wiring board disclosed in this reference has a semiconductor chip as a component to be buried in addition to the passive component such as a chip condenser (chip capacitor). By burying the semiconductor component such as a semiconductor chip, an added value as the component built-in wiring board increases markedly in comparison with a case having the passive component only.
In a case where semiconductor components are buried and mounted in the wiring board, the wiring board itself is not so thick even though it is a multilayer board in these years, and normally it is necessary to use one, for example, a bare chip which is as thin as possible. When the bare chip is used, it is advantageous as described in the above reference under the constraint of the thickness to mount it with face down on the inner-layer wiring pattern of the wiring board. The technology to mount the semiconductor chip with face down on the wiring pattern is generally known as the flip-chip connection and can be incorporated.
The flip-chip connection includes the technology of aligning the connection pads having a fine pitch formed on the semiconductor chip with the lands of the wiring pattern, and the size of the work having the wiring pattern cannot be increased considerably to ensure the positional accuracy. Meanwhile, the technology of mounting the passive components such as chip capacitors on the wiring pattern is a so-called surface mounting technology using a solder or a conductive adhesive agent as the connecting member between the components and the wiring pattern. The alignment accuracy of the components to the wiring pattern in this case may be lower than that of the flip-chip connection. Therefore, production facilities for relatively large works can be used considering productivity.
Therefore, for the component built-in wiring board which has plural kinds of components such as passive components and semiconductor components buried and mounted in mixture in the wiring board, the surface mounting technology is used to mount the passive components, and the flip-chip connection technology is used to mount the semiconductor chips. Since separate processes are required, there is caused an issue to improve the productivity. The flip-chip connection is also disadvantageous in improving the productivity because it cannot conform to a large work.
Also, an example of a component built-in wiring board that a semiconductor chip is buried and mounted by the flip connection is described in the following JP-A 2003-197849 (KOKAI). By the flip connection of the semiconductor chip (bare chip), the thickness produced by mounting is saved to almost the minimum, and thus the flip connection becomes an important method when the semiconductor element is built in the wiring board.
For example, the flip connection can be made by further forming Au bumps on the terminal pads formed on the semiconductor chip and press-contacting them to a wiring pattern formed on the wiring board with an adhesive agent (underfill resin). What is considered here is to secure a low resistance connection between the Au bumps and the wiring pattern and its connection reliability. Therefore, the wiring pattern surface is required to have high cleanness, and as a commonly-performed method, the Au layer is formed by plating also on the surface of the wiring pattern.
Generally, to perform the flip connection of the semiconductor chip on the main surface of the wiring board, a protective layer such as a solder resist is formed on the wiring pattern excluding the portion which is used for connection, and then the Au plated layer is formed on the portion used for connection. Thus, Au plating which is not necessarily inexpensive can be applied to only a minimum area.
In a case where the semiconductor chip is buried in the wiring board and flip-connected, there are some differences from the flip connection of the semiconductor chip to the main surface described above. First, there is an influence that the solder resist becomes part of the insulating layer which is an inner layer. Generally, adhesiveness between the solder resist and the insulating plate material used for the wiring board is not as strong as that between the insulating plate materials. Therefore, when a configuration that the solder resist as the inner layer is omitted is adopted, it is necessary to apply a large area of Au plating, thus affecting the manufacturing cost. Adhesion between the Au plated layer and the insulating plate material is not necessarily strong, remaining an issue to be solved.
Moreover, an example of a component built-in wiring board having a semiconductor chip buried and mounted is described in the following JP-A 2003-197849 (KOKAI). As described in this reference, its built-in structure can be made simpler by directly burying and mounting the semiconductor chip (bare chip) in the wiring board.
However, it is impressive in recent years that the semiconductor chip is being made to have multiple terminals and a narrow pitch, and when such a state-of-the-art semiconductor chip is intended to be directly buried and mounted in a multilayer wiring board, there occurs a situation in which a general wiring rule of a buildup substrate cannot be used. For example, there is a case that the semiconductor chip has a terminal pitch of 50 μm or below, and a patterning method of a general buildup substrate is limited to a pitch of about 70 μm even by the latest technology.
Also, even though the wiring rule of the wiring board becomes conformable, the size of a work that a mounting apparatus can deal with is limited. To manufacture the printed wiring board, it is preferable to increase the size of one work as large as possible for improvement of working efficiency. Thus, multiple products are arranged in one work and manufactured at the same time. For example, the work size is 400 mm×500 mm. But, when the work is large, precision indexes for dimensional accuracy, positional accuracy and pattern finishing accuracy of the substrate become worse. Therefore, the mounting apparatus necessarily becomes to be limited for a small work size as the wiring rule of the wiring board becomes narrower. Thus, manufacturing efficiency becomes worse.
In addition, when the semiconductor chip is directly buried and mounted in the wiring board, the semiconductor chip cannot be screened solely, and the screening is performed in a process after the component built-in wiring board is formed. Thus, the manufacturing process for the wiring board is often wasted because of a defect in the semiconductor chip, causing a cost management issue.
Patent Reference 1: JP-A 2003-197849 (KOKAI)